Negative Capacitance for Ultra Low Power MOSFETs
Sayeef Salahuddin, Professor
Electrical Engineering and Computer Science
Applications for Spring 2025 are closed for this project.
It is widely believed that the rate of change in current in conventional MOSFETs cannot be decreased below 60 mV/decade. This means that to change every decade of current one must apply at least 60 mV. As a result, the power supply voltage in modern MOSFETs cannot be reduced below a certain point and it has been indicated that unless a solution is found, the scaling of MOSFETs will die a thermal death. Recently, we have shown theoretically that if a gate stack can be constructed with negative differential capacitance, the rate of change in current can be reduced below 60 mV/decade. In this project we shall try to build this gate stack. The undergraduate researchers will be helping with material growth and lithography at the nanometer scale.
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